The creation of complex integrated circuits and semiconductor devices can be a very expensive undertaking given the large number of hours of sophisticated engineering talent involved in designing such devices. Additionally, integrated circuits can include read-only memories into which software, in the form of firmware, is encoded. Further, integrated circuits are often used in applications involving the encryption of information, and therefore in order to keep such information confidential, it can be desirable to keep such devices from being reverse engineered. Thus, there can be a variety of reasons for protecting integrated circuits and other semiconductor devices from being reversed engineered.
In order to keep the reverse engineer at bay, different techniques are known in the art to make integrated circuits more difficult to reverse engineer. One technique that is used is to make the connections between transistors difficult enough to determine that the reverse engineer must carefully analyze each transistor (in particular, each CMOS transistor pair for CMOS devices), and not use automatic circuit and pattern recognition techniques in order to reverse engineer the integrated circuit. Since integrated circuits can have hundreds of thousands or even millions of transistors, forcing the reverse engineer to carefully analyze each transistor in a device can effectively frustrate the reverse engineer's ability to reverse engineer the device successfully.
The prior art techniques mentioned above, if successful, will force the reverse engineer to study the metal connections to try to figure out the boundaries of standard circuits and to try to figure out their function. For example, gate connections may utilize the polysilicon layer (the first polysilicon layer in a process having two or more polysilicon layers) and the reverse engineer would look for these contacts, knowing that these gate contacts are typically the input to transistors and hence to a standard circuit. In addition, the source and drain contacts are made to the substrate via metal interconnects. One way in which the reverse engineer might work would be to look for cell boundaries by means of looking for silicon-to-gate poly metal lines, as these suggest the possibilities for contacts between the output (the drain contact) from one transistor cell into the input (the gate contact) of a next transistor cell. If this can be done, the reverse engineer can define cell boundaries by these silicon-gate poly lines. Then, by noting the cell boundaries, the reverse engineer can find the cell characteristics (for example, size and number of transistors) and from this make reasonable assumptions as to the cell's function. In addition to cell boundaries, the reverse engineer may also rely upon the size of the transistor and its location. For example, P-channel devices (PMOS) are larger than N-channel devices (NMOS), and all PMOS devices are grouped in one row while all NMOS devices are grouped in a different row. This information could then be stored in a database for automatic classification of other similar cells.
It is an object of this invention to make reverse engineering more difficult and, in particular, to force the reverse engineer to study implants under the gates. It is believed that this will make the reverse engineer's efforts all the more difficult by making it very time consuming, and perhaps making it exceedingly impractical, if not impossible, to reverse engineer a chip employing the present invention. The present invention can be used harmoniously with techniques disclosed in the prior United States patents and patent applications identified above to further confuse the reverse engineer.
FIG. 1a depicts a simplified cross-section of a prior art single well CMOS device. In a NMOS device, shown on the left, an active region 16a is typically a n-type source region, while active region 18a is typically a n-type drain region disposed in a p-type substrate 12. A gate 20a may be manufactured out of a layer of polysilicon 19 disposed upon a layer of gate oxide 21. The gate 20a is disposed between the two active regions 16a, 18a. Field Oxide 10 isolates the NMOS device from the PMOS device of the CMOS pair and other semiconductor devices within the IC. In a PMOS device, shown on the right, an active region 16b is typically a p-type source region, while active region 18b is typically a p-type drain region disposed in a n-type well 42 of the substrate 12. A gate 20b may be manufactured out of a layer of polysilicon 19 disposed upon a layer of gate oxide 21. The gate 20b is disposed between the two p-type active regions 16b, 18b. The n-type well 42 isolates the p-type active regions 16b, 18b from the p-type substrate 12.
FIG. 1b depicts a simplified cross-section of another prior art CMOS device. Two major goals in the semiconductor industry are to increase the density and to increase the speed of digital or analog integrated circuits (ICs). Increasing the density means using smaller channel lengths and widths. In order to satisfy the conditions such as separation of highly integrated fine or minute elements of a semiconductor device, some n-type devices of a CMOS pair having a substrate of a first conductivity type have a well of the same conductivity type as the substrate. FIG. 1b is a simplified cross-sectional view of such a prior art CMOS device, the NMOS device being shown on the left while the PMOS device is shown on the night. The NMOS device has a well 14 of a first conductivity type formed in the first conductivity type semiconductor substrate 12. In the example shown in FIG. 1b, the substrate 12 is a p-type semiconductor substrate and well 14 is a p-type well. The source region 16a and drain region 18a of the NMOS device have a second conductivity and are preferably of n-type. Field Oxide 10 isolates the NMOS device from the PMOS device in the CMOS pair and also isolates the semiconductor device from other semiconductor devices within the IC. The gates 20a, 20b are manufactured out of a layer of polysilicon 19 disposed on a layer of gate oxide 21. In the PMOS device, the source region 16b and drain region 18b are p-type. Under the source region 16b and drain region 18b is a n-type well 42.
The present invention preferably makes use of a standard CMOS manufacturing process called a “double well process” in which the semiconductor substrate of a first conductivity has a well having a first conductivity type, and a well having a second conductivity type. One skilled in the art will appreciate, after reading this patent, that the present invention may also make use of other CMOS processes that are not double well processes. Masks are used to determine the location and shapes of the first conductivity type wells and the second conductivity type wells.
As will be seen, changing the location of the different wells forms a conduction path between two active regions, such as the source and drain. Thus, the resulting semiconductor device will be permanently ON for any reasonable gate voltage. Therefore, with the present invention, the circuit may be constructed to look the same as some conventional circuits, but the functionality of selected transistors will be quite different and therefore the circuit will function quite differently from the circuit that it visually mimics. Since the reverse engineering process looks for repeating patterns of circuit devices (as seen from a top or plan view) and assumes that all repeating patterns reflect the same circuit functions, the reverse engineer is apt to assume an incorrect function when trying to copy the original integrated circuit. Thus, the real functionality of the integrated circuit in which the present invention is used is hidden. Of course, if this technique of making a pattern of transistors mimic a conventional circuit but perform a different function is used hundreds or thousands of times in a complex integrated circuit having perhaps millions of transistors, the reverse engineer ends up with not only a device which does not work, but also a daunting task of trying to figure out what went wrong with the assumptions that he or she made in analyzing the chip to be reverse engineered. This additional effort, if undertaken, forces the reverse engineer to spend additional time trying to determine how the chip in question is really configured.
The present invention not only provides a device and method that will confuse the reverse engineer, but it also provides a simpler path to implementation than other methods of inhibiting the reverse engineering process. The technique disclosed herein may be utilized to modify the library design of a particular vendor as opposed to forming a completely new and different appearing library. Thus, those skilled in the art will appreciate that the cost and time associated with the present invention is less than other methods used to inhibit integrated circuits from being reverse engineered.
Note that the present invention might only be used once in a thousand of instances of what appears to be a semiconductor device or a pattern of devices on the chip in question, but the reverse engineer will have to look very carefully at each semiconductor device or pattern knowing full well that for each semiconductor device or pattern that he or she sees, there is a very low likelihood that it has been modified by the present invention. The reverse engineer will be faced with having to find the proverbial needle in a haystack.
Briefly, and in general terms, the present invention comprises a method of camouflaging an integrated circuit for the purpose of deterring a reverse engineer, wherein a well of the same type as the source and drain regions is placed under the gate in contact with the source and drain region.
In another aspect, the present invention provides for camouflaging an integrated circuit structure. The integrated circuit structure is formed by a plurality of wells. The well under the gate being disposed adjacent to the same type source and drain regions.